Processing technology has achieved significant increases in processing speed, yet, nevertheless for speech processing, signal processing and image processing systems involving numerous accesses to non-integrated memory devices, the gain in processing speed has been largely offset by relatively slow access times to non-integrated memory devices.
This problem of slow access times is further aggravated by the direction of conventional memory technology toward increasing memory device density. With increased memory device density, the maximum bandwidth of a system decreases because the multiple bus architecture are less practical. For example, in order to store a 480.times.240, 16-bit image, a graphics application having two 1-megabyte devices achieves one-quarter of the bandwidth then a graphics application having eight 256-kilobyte memory devices.
In accordance with the technique for adjusting the shortcomings, overall system throughput is increased by off-loading time-intensive tasks from a host processor to an Application-Specific Integrated Circuit (ASIC). Nevertheless, one ASIC is used for each function to be off-loaded and memory is dedicated for each ASIC. Accordingly, a higher overall system cost results. Moreover, the system throughput is increased only for a specific task to which the ASIC is directed rather than for tasks in general. Further, the memory dedicated to the ASIC is usually not accessible by the host processor even if the attached ASIC is idle, and well-developed software is needed for "seamless integration". In another technique, a co-processor off-loads tasks from a host processor, and system memory is shared between the host processor and the co-processor. Nevertheless, the total system bandwidth is decreased by arbitration between the host processor and the co-processor. Further, well-developed software is required to comprehensively achieve "seamless" integration of the co-processor. In response to the practical limits on the execution speed of a single processor, other techniques have attempted to increase throughput by partitioning and parallel processing with multiple processors. Nevertheless, such multiprocessing systems have been limited by difficulties in designing software support routines and in developing communication protocols. Thus, a need has arisen for a method and system for improved processing, in which existing systems are readily upgraded by externally interfacing to a memory device. Further, a need has arisen for a method and system for improving processing which the memory device is externally interfaced as a standard memory device. Also, a need has arisen for a method and system for improved processing, in which parallel processing can be more readily achieved such that system throughput is increased.